In general, flash memory has been developed to achieve the advantages of both a related art erasable programmable read only memory (EPROM) and a related art electrically erasable PROM (EEPROM). The flash memory is capable of electrically programming and erasing data, and its manufacturing unit costs are relatively low because of its simple manufacturing processes and miniaturized chip size.
Additionally, the flash memory has characteristics of a random access memory (RAM) in that the flash memory is a non-volatile memory, retaining its stored data even when there is no power supply, and is also capable of electrically programming and erasing information in a system. Therefore, the flash memory is often used as a memory device replacing a memory card or a hard disk of portable electronic devices.
In this flash memory, the programming of data may be performed by injecting hot electrons. That is, if hot electrons occur in a channel by an electric potential difference between a source and a drain, hot electrons having an energy of more than 3.1 eV (i.e., an electric potential barrier between polycrystalline silicon and an oxide layer constituting a control gate) are transferred into and stored in a floating gate due to a high electric field of a control gate.
Hot electron generation is unavoidable in certain flash memory devices that are designed to generate these hot electrons. However, because hot electrons may deteriorate the related art metal oxide silicon (MOS) device, the device needs to be designed to suppress device deterioration, if possible.
In this flash memory, a critical dimension (CD) of a gate is a very important factor in determining device characteristics during the forming of a gate pattern.
Usually, in order to form the gate pattern, a polysilicon layer is formed on a semiconductor substrate, and an anti-reflection layer and a photoresist pattern are formed on the polysilicon layer. Then, the anti-reflection layer and the polysilicon layer are patterned by using the photoresist pattern as a mask.
FIG. 1 is a cross-sectional view illustrating a part of semiconductor device manufacturing processes.
A semiconductor substrate 10 includes a cell area CA, a peripheral area PA around the cell area CA, and an interface area IA between the cell area CA and the peripheral area PA.
A device isolation layer pattern 11 is formed in the semiconductor substrate 10 to define an active area where devices are to be formed.
A flash memory device is formed in the cell area CA. A floating gate 13 is formed on the semiconductor substrate 10, and a polysilicon layer 15 for a control gate is formed on the floating gate 13.
A hard mask layer 17, an anti-reflection layer 19, and a photoresist pattern 20 are sequentially stacked on the polysilicon layer 15 in order to form a control gate by patterning the polysilicon layer 15 using the photoresist pattern 20 as a mask.
However, because the floating gate 13 is formed only in the cell area CA, there is a height difference between the cell area and the interface area. Thus, a thinning phenomenon occurs, in which the anti-reflection layer 19 becomes thinner as it approaches from the center to the edge in the cell area CA.
The light reflectivity of the anti-reflection layer 19 is affected by the thinning phenomenon, and varies at the edge of the cell area (due to the thickness change of the anti-reflection layer 19) during a photolithography process to pattern the polysilicon layer 15 to form a control gate. Therefore, the CD of the photoresist pattern 20 is reduced.
If the CD of the photoresist pattern 20 is reduced, the photoresist pattern 20 may collapse, and a defective memory device may be formed, or it may prevent uniform adjustment of the CD of the control gate. These limitations affect wafer yield directly and substantially, and may also deteriorate device reliability.